The present invention is related to charge transfer circuits of the type comprising first and second charge storage capacitors and a charge transfer transistor for transferring a plurality of discrete packets of charge from the first to the second charge storage capacitor. Charge transfer circuits of the foregoing type are particularly useful in monolithic analog to digital converters such as those described in U.S. Pat. application Ser. No. 628,542, filed Nov. 3, 1975, now abandoned and replaced by application Ser. No. 853,115, filed Nov. 21, 1977 U.S. Pat. No. 4,145,689, and assigned to the assignee of the present application. Exemplary of several applications of such circuits is U.S. Pat. No. 3,819,954 which discloses a charge transfer delay line circuit.
While the uses of charge transfer circuits are varied, a common requirement of charge transfer analog to digital converters is that an equal amount of charge be transferred to the second charge storage capacitor during each charge transfer operation. This requirement is especially crucial in uses involving analog to digital converters which rely on an accurate count of the number of metered charge packets required to change the charge stored in the second charge storage capacitor from a first to a second level.
In applications of the latter type, a MOSFET transistor is operated in the "shelf" transistor mode so as to transfer a metered charge packet, whose magnitude is a function of the gate voltage of the MOSFET less its threshold voltage from the first to the second capacitor. To obtain proper results, the magnitude of the charge packet transferred by the MOSFET is ideally constant. In actual practice, however, the size of the charge packets varies, for example, as a function of both a thermally induced leakage current in the semi-conductor substrate in which the first and second capacitors and the charge transfer transistors are preferably formed and variations in the magnitude of the threshold voltage of the MOSFET. These latter variations are also a function of temperature.
The prior art has disclosed several circuits which compensate for variations in the magnitude of the charge packets due to changes in the magnitude of the thermally induced leakage current. The present invention is designed to compensate for errors resulting from changes in the magnitude of the threshold voltage.